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| For Audio Equipment MN66271RA Signal Processing LSI for Compact Disc Players Overview The MN66271RA is a CD signal processing LSI that, on a single chip, combines optics servos for the CD player (focus, tracking, and traverse servos), digital signal processing (EFM demodulation and error correction), digital servo processing for the spindle motor, digital filter, and D/A converter, so thus covers all signal processing functions from the head's RF amplifier onward. (Spindle motor servo) CLV digital servo (Audio circuits) Digital filter using 8 times oversampling Built-in D/A converter (1-bit D/A converter) Built-in differential operational amplifier (PWM output) (Other) Built-in playback pitch control function (13%) Operating voltage 4.5 to 5.5 V Features (Optics servo) Focus, tracking, and traverse servos Automatic adjustment functions for FO/TR gain, FO/TR offset, and FO/TR balance Built-in D/A converter for drive voltage output Built-in dropout countermeasures Anti-shock functions Built-in track cross counter Support for both linear motor and screw-based traverse mechanisms Support for 3- and 1-beam systems Digital Signal Processing (Digital signal processing) Built-in DSL and PLL Frame synchronization detection, holding, and insertion Subcode data processing Subcode Q data CRC check Built-in subcode Q data register CIRC error detection and correction C1 decoder: duplex error correction C2 decoder: triplex error correction Built-in 16-K bits of RAM for use in deinterleaving Audio data interpolation Averaging or retention of previous values Soft muting Digital attenuation (256 levels) Software attenuation (256 levels) Audio data peak level detection function Automatic cuing detection function Digital audio interface (EIAJ format) Audio data serial interface Applications CD Players MN66271RA Pin Assignment For Audio Equipment 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 BYTCK CLDCK FCLK IPFLAG FLAG CLVS CRC DEMPH RESY RST2 TEST AVDD1 OUTL AVSS1 OUTR RSEL CSEL PSEL MSEL SSEL 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD X2 X1 VSS SBCK SUBC PDO PCK EFM AVSS2 AVDD2 VCOF PLLF DSLF DRF IREF ARF WVEL PLAY TES LDON BDO RFDET TRCRS OFT VDET RFENV TE FE TBAL FBAL VREF FOD TRD KICK ECS ECM PC TVD TRV BCLK LRCK SRDATA DVDD1 DVSS1 TX MCLK MDATA MLD SENSE FLOCK TLOCK BLKCK SQCK SUBQ DMUTE STAT RST SMCK PMCK (TOP VIEW) QFS080-P-1414 For Audio Equipment Block Diagram RST2 MN66271RA 70 8 TIMES OVER SAMPLING DIGITAL FILTER DIGITAL DEEMPHASIS PWM (R) 51 AVSS2 50 AVDD2 75 - + OUTR 1 BIT DAC LOGICS 73 PWM (L) - + OUTL DIGITAL AUDIO INTERFACE CLVS CRC BLKCK CLDCK SBCK SUBC DEMPH RESY 66 67 13 62 56 55 68 69 SUBCODE BUFFER CIRC ERROR CORRECTION 16K SRAM DEINTERLEAVE 74 AVSS1 72 AVDD1 65 FLAG 64 IPFLAG 6 EFM DEMODULATION SYNC INTERPOLATION SUBCODE DEMODULATION 80 SSEL 14 SQCK 15 SUBQ PCK EFM PLLF DSLF IREF DRF ARF RSEL PSEL 53 52 48 47 45 46 44 76 78 TX CLV SERVO 24 23 ECM PC VCO 9 MLD 7 MCLK 8 MDATA 49 VCOF 61 BYTCK 19 SMCK 63 FCLK 20 PMCK 77 CSEL 79 MSEL 59 X2 58 X1 17 STAT 2 LRCK 3 SRDATA 1 BCLK 16 DMUTE 21 TRV 26 KICK 29 V 25 REF ECS 22 TVD 27 TRD 28 FOD 31 TBAL 30 FBAL 41 TES 12 TLOCK 11 FLOCK 42 PLAY 40 LDON 43 WVEL 10 SENSE INTERPOLATION SOFT MUTING DIGITAL ATTENUATION PEAK DETECT AUTO CUE DSL*PLL TIMING GENERATOR PITCH CONTROL VCO MICROCOMPUTER INTERFACE SERVO CPU A/D CONVERTER 60 57 4 5 18 71 32 33 34 INPUT PORT 37 35 39 SERVO TIMING GENERATOR 38 36 OFT TE VDET RFENV TRCRS RFDET VDD VSS DVDD1 DVSS1 RST TEST FE BDO OUTPUT PORT D/A CONVERTER MN66271RA Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol BCLK LRCK SRDATA DV DD1 DVSS1 TX MCLK MDATA MLD SENSE FLOCK TLOCK BLKCK SQCK SUBQ DMUTE STAT RST SMCK PMCK TRV TVD PC ECM ECS KICK TRD FOD VREF FBAL TBAL FE TE RFENV VDET OFT TRCRS RFDET BDO LDON I/O O O O I I O I I I O O O O I O I O I O O O O O O O O O O I O O I I I I I I I I O For Audio Equipment Function Description SRDATA bit clock output Left/right channel discrimination signal output Serial data output Power supply for digital circuits Ground for digital circuits Digital audio interface output signal Microcomputer command clock input (Data is latched at rising edge.) Microcomputer command data input Microcomputer command load signal input. Focus servo convergence signal. Tracking servo convergence signal. External clock input for subcode Q register Subcode Q data output Muting input. Reset input. "H" level: muting. "L" level: reset. Status signal (CRC, CUE, CLVS, TTSTOP, FCLV, and SQOK) If MSEL is at "H" level, 8.4672 MHz clock signal output. If MSEL is at "L" level, 4.2336 MHz clock signal output. 88.2 kHz clock signal output Traverse forced feed output Traverse drive output Spindle motor ON signal. Spindle motor drive signal (forced mode output) Spindle motor drive signal (servo error signal output) Kick pulse output Tracking drive output Focus drive output Reference voltage for DA output (TVD, ECS, TRD, FOD, FBAL, and TBAL) Focus balance adjustment output Tracking balance adjustment output Focus error signal input (analog input) Tracking error signal input (analog input) RF envelope signal input (analog input) Vibration detection signal input. Offtrack signal input. Track cross signal input RF detection signal input. Dropout signal input. Laser ON signal output. "L" level: detected. "H" level: dropout. "H" level: ON. "H" level: vibration detected. "H" level: offtrack. "L" level: ON. 3-State "L" level: load. "L" level: convergence. "L" level: convergence. Sense signal output (OFT, FESL, NACEND, NAJEND, POSAD, and SFG) Subcode block clock signal (fBLKCK =75 Hz, normal playback) For Audio Equipment Pin Descriptions (continued) Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Symbol TES PLAY WVEL ARF IREF DRF DSLF PLLF VCOF AV DD2 AV SS2 EFM PCK PDO SUBC SBCK VSS X1 X2 VDD BYTCK CLDCK FCLK IPFLAG FLAG CLVS CRC DEMPH RESY RST2 TEST AV DD1 OUTL AV SS1 OUTR RSEL CSEL I/O O O O I I I I/O I/O I/O I I O O O O I I I O I O O O O O O O O O I I I O I O I I MN66271RA Function Description Tracking error shunt signal. "H" level: shunt. Play signal output. RF signal input Reference current input pin DSL bias pin DSL loop filter pin PLL loop filter pin VCO loop filter pin for pitch control Power supply for analog circuits (DSL, PLL, and D/A converter output) Ground for analog circuits (DSL, PLL, and D/A converter output) EFM signal output PLL derived clock output with fPCK=4.3218 MHz Phase comparator output for EFM and PCK signals Subcode serial output data output Serial clock input for subcode serial output Ground for oscillator circuit Crystal oscillator circuit input pin. f=16.9344 MHz. Crystal oscillator circuit output pin. f=16.9344 MHz. Power supply for oscillator circuit Byte clock signal output Subcode frame clock signal output pin (fCLDCK=7.35 kHz) Crystal frame clock signal output (fFCLK=7.35 kHz) Interpolation flag signal output. Flag signal output Spindle servo phase synchronization signal output. "H" level: CLV. "L" level: rough servo. Subcode CRC check result output. De-emphasis detection signal output. Frame resynchronization signal. "H" level: OK. "L" level: no good. "H" level: ON. "H" level: synchronized. "L" level: out of sync. Reset pin for stopping operation of circuits past D/A converter Test pin. audio outputs) Left channel audio output Ground for analog circuits (common use for left and right channel audio outputs) Right channel audio output RF signal polarity selection pin. Test pin. "H" level: bright level is "H. "L" level: bright level is "L. Keep this pin at "L" level. Keep this pin at "H" level. Power supply for analog circuits (common use for by left and right channel "H" level: interpolation. "H" level: play. Double-speed status signal output. "L" level: double-speed. MN66271RA Pin Descriptions (continued) Pin No. 78 79 Symbol PSEL MSEL I/O I I For Audio Equipment Function Description Test pin. Frequency selection pin for SMCK pin output. "H" level: SMCK=8.4672 MHz. "L" level: SMCK=4.2336 MHz. Keep this pin at "L" level. 80 SSEL I SUBQ pin output mode selection pin. "H" level: buffered subcode Q mode. Package Dimensions (Unit: mm) QFS080-P-1414 16.20.2 14.00.2 60 61 41 40 0.825 14.00.2 80 21 1 0.65 20 2.00.2 0.3 -0.05 2.10.3 +0.10 16.20.2 1.10.1 0 to 10 0.550.1 +0.10 -0.05 0.15 SEATING PLANE 0.10.1 0.15 |
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